1. Field of the Invention
The present invention generally relates to semiconductor wafers. More particularly, the present invention relates to dummy structures in trenches or vias of semiconductor wafers.
2. Description of the Related Art
In general, semiconductor devices are manufactured or fabricated on disks of semiconducting materials called wafers or slices. More particularly, wafers are initially sliced from a silicon ingot. The wafers then undergo multiple masking, etching, and deposition processes to form the electronic circuitry of semiconductor devices.
In particular, multiple masking and etching processes can be used to form recessed areas in a wafer, such as trenches, vias, and the like. In some applications, these recessed areas can form wide trenches. Deposition processes can be used to deposit metal onto both the wide trenches and non-recessed areas of the wafer. After deposition, the metal can be removed from the non-recessed areas of the wafer, such that the metal left in the wide trenches can form interconnections. However, because of the width of the wide trenches, when the metal is removed from the non-recessed areas, a portion of the metal deposited in the wide trenches can also be removed beyond a desirable depth. This over-removal, called dishing, can reduce the cross-sectional area of the interconnections, thereby increasing the resistance of the interconnections. This increased resistance can cause reliability problems in the semiconductor device.
Accordingly, forming dummy structures within the wide trenches has been used to reduce dishing when chemical mechanical polishing (CMP) is used to remove the metal from the non-recessed areas of the wafer. In particular, the dummy structures can prevent a CMP polishing pad from moving past the dummy structures and overpolishing metal in the wide trenches. However, dishing can still occur if electropolishing is used to remove metal from the non-recessed areas, even when the wide trenches include dummy structures.
The present invention relates to electropolishing a metal layer on a semiconductor wafer. In one embodiment of the present invention, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recessed area, where the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer. A metal layer is then formed to fill the recessed area and cover the non-recessed area and the plurality of dummy structures. The metal layer is then electropolished to expose the non-recessed area. In one embodiment, a portion of the non-recessed area is then removed.